Khóa học Signal and power integrity simulation – Lớp offline

4.000.000 ₫

Thời lượng: 30 giờ

Giáo trình: 15 bài giảng

Địa chỉ học:
Cơ sở 1: 546 Ngô Gia Tự, Phường 9, Quận 5, TP.HCM
Cơ sở 2: 220/66 Xô Viết Nghệ Tĩnh, Phường 21, Quận Bình Thạnh, TP.HCM
Cơ sở 3: 403 Lý Thường Kiệt, Phường 8, Quận Tân Bình, TP.HCM

DANH MỤC :

Mô tả khóa học

Hình ảnh lớp học

Cảm nhận học viên

Khóa học SIGNAL AND POWER INTEGRITY SIMULATION

Khóa học hướng dẫn bạn khảo sát các nhân tố ảnh hưởng đến tính toàn vẹn tín hiệu, bao gồm: transmission lines, reflections, inductance, ground bounce, differential pairs, losses, terminations, routing, discontinuities, impedance, crosstalk, and EMC.
Khóa học hướng dẫn cách mô phỏng việc truyền tín hiệu có nhiễu và đưa ra giải pháp để giảm nhiễu tối ưu.

Thực hành trực tiếp trên các project thực tế: Mô phỏng SI, PI các project theo quy trình đầy đủ.

Khóa học này dành cho học viên đã biết các phần mềm thiết kế PCB như:

Altium
Allegro
Protues
Protel
KiCad,….

Nội dung khóa học

Bài 1:

Overview about the general SI knowledge in PCB design.
Introduce about the RAM design field in PCB design và SI simulation.

Bài 2:

Overview about the Cadence Sigrity Tool belong to SI field.
Introduce about the DDR model (netlist block, controller block, memory block, source block, ...)
Introduce about the Ibis models (in controller & in memory) in SI system.

Bài 3:

Run template file 1 DDR design project by Cadence Sigrity.
+ Review about the JEDEC DDR Layout specification.
+ Review DDR Layout Board on Speed 2000 tool, Run ERC to get the impedance results and coupling results.

Bài 4:

Run template file 1 DDR design project by Cadence Sigrity. (Continue)
+ Build model in systemSI tool, view waveform.
+ Investigate the final results & make report, feedback and modify to layout board.

Bài 5:

Run allCA details information about the DDR4 1Rank design. (template file)
+ Initial run sim for original design. (investigate the ringing back margin, eye diagram, timing)
+ Review about the mis-match (impedance and length) in high-speed signals after run SI simulation.

Bài 6:

Run allCA details information about the DDR4 1Rank design. (template file) (To be continue)
+ Layout modification. (trace width, spacing rule - impedance matching and reduce coupling)
+ Layout modofication. (trace length - balance timing -> Eye diagram improvement)
+ Final run SI simulation, compare the performance with original design.
+ Final STEP: increase the SPEED on DDRx design as possible.

Bài 7:

Run allCA details information about the DDR4 1Rank design. (template file) (To be continue)
+ Layout modification. (trace width, spacing rule - impedance matching and reduce coupling)
+ Layout modofication. (trace length - balance timing -> Eye diagram improvement)
+ Final run SI simulation, compare the performance with original design.
+ Final STEP: increase the SPEED on DDRx design as possible.

Bài 8:

Run allCA details information about the DDR4 1Rank design. (template file) (To be continue)
+ Layout modification. (trace width, spacing rule - impedance matching and reduce coupling)
+ Layout modofication. (trace length - balance timing -> Eye diagram improvement)
+ Final run SI simulation, compare the performance with original design.
+ Final STEP: increase the SPEED on DDRx design as possible.

Bài 9:

Run allCA details information about the DDR4 1Rank design. (template file) (To be continue)
+ Layout modification. (trace width, spacing rule - impedance matching and reduce coupling)
+ Layout modofication. (trace length - balance timing -> Eye diagram improvement)
+ Final run SI simulation, compare the performance with original design.
+ Final STEP: increase the SPEED on DDRx design as possible.

Bài 10:

Run allCA details information about the DDR4 1Rank design. (template file) (To be continue)
+ Layout modification. (trace width, spacing rule - impedance matching and reduce coupling)
+ Layout modofication. (trace length - balance timing -> Eye diagram improvement)
+ Final run SI simulation, compare the performance with original design.
+ Final STEP: increase the SPEED on DDRx design as possible.