Khóa học System Verilog and UVM cơ bản

Bài 1: Verification Process

• • Design Verification Flow
• • Test plan
• Lab:
• • Create direct test for Async FIFO design
• • Practice with tools: Verdi, VCS

Bài 2: Overview about UVM

• Object-Oriented Programming in System Verilog:
• • OOP terminology
• • Create a class for testbench component
• Introduction to UVM:
• • UVM component
• • UVM phase
• Lab: Investigate an example of UVM testbench

Bài 3: Project 1: Build Simple UVM environment for Async FIFO design

• • Investigate design specification
• • Create test plan
• • Build environment’s components

Bài 4: Project 1 (cont): Create test and verify the DUT